It is common for manufacturers of computer processors to specify that current be supplied at a plurality of voltages. For example, a computer processor may require voltage at 3.3 Volts for external I/O circuits, and a smaller second voltage amount, referred to as the core voltage, for core circuitry. Thus, a processor can communicate with the motherboard at one voltage, and operate its internal circuitry at the reduced voltage.
On starting up a computer system, the core voltage supplied by the motherboard ramps up from zero when the power is switched on and at some points reaches a minimum acceptable voltage level close to the core voltage specified by the manufacturer. It is important that the processor not begin operating until the power has reached this minimum acceptable voltage level. Therefore, to determine when the minimum acceptable voltage level is reached, a “Power OK” (POK) signal is generated. Typically, the POK signal will be asserted when the core voltage reaches the minimum acceptable voltage, thereby indicated to the processor that it is ok to begin operation.
As computer processors are manufactured with smaller and smaller transistors, conductors, and other features, the problem of voltage leakage across closed transistor gates and cross talk has been met by taking a variety of measures. One significant measure taken by processor designers and manufacturers is the increasingly lowered core voltage. With reduced voltage, less current leaks across the closed transistors, which results in more efficient processors that dissipate less power in the form of heat.
The continuing reduction of core voltage requirements has caused a problem for circuit board manufacturers who provide circuit boards supporting a variety of processors, and therefore a variety of core voltages. With the wide range of core voltage requirements of older and newer processors, and with the expectation of even further reduction in core voltages, it has been necessary to provide core voltages that vary from, for example, 0.775 Volts to 1.550 Volts with increments of as little as 0.025 Volts.
To provide an accurate POK signal with such a broad range of core voltages, designers have resorted to dividing up the range of core voltages into segments, e.g., four segments, each having a corresponding reference voltage generated using a distinct voltage divider. Each voltage divider supplies a specified reference voltage output between two resistors connected in series between a main 3.3 Volt supply and ground. The reference voltage corresponding to the segment in which the core voltage lies is selected using a multiplexer. The selected reference voltage is then compared with the core voltage using a comparator, which gives a logic high when the core voltage exceeds the selected reference voltage. The output of the comparator is passed through a delay circuit to delay by a selected delay amount, e.g., 140 to 280 milliseconds. The output of the delay circuit is the POK signal. In one embodiment, the POK signal changes to a logic high after the comparator output changes with a 200 millisecond delay.
A problem with previous POK signal generators has been a lack of accuracy that has been traced to the initial voltage input. Depending on the main power supply, it is possible that during system startup, voltages in the main 3.3 Volt rail will fluctuate somewhat due to high current draws from various components such as main memory. Since the reference voltages are taken by dividing the main 3.3 Volt supply, the reference voltage will also fluctuate, which could adversely affect the proper timing of the POK signal, and could potentially lead to errors.
There therefore exists a need to more reliably determine when the core voltage reaches the target core voltage specified by the processor manufacturer.